1. Field of the Invention
The invention pertains generally to computers. More particularly, the invention pertains to cache coherency in a chip multiprocessor.
2. Description of the Related Art
Multi-core computer architecture typically includes multiple processors on a single chip, referred to as a chip multiprocessor (CMP), and the chip also includes cache memory (referred to simply as ‘cache’). Each processor has its own dedicated on-chip cache memory for fast access to the code being executed and the data being operated upon. The chip typically also has another level of cache that is shared by all the processors, and at least one additional level of memory exists off-chip (either main memory or a higher level of common cache) that serves as a uniform data source for the on-chip cache. Each processor may modify a cache line within its own dedicated cache by writing to one or more locations within its own dedicated cache. However, if multiple processors are operating with the same cache line, one processor may modify the cache line in its own dedicated cache while the same cache line in other dedicated caches remains unchanged. This creates a problem with cache coherency—not all dedicated caches will have the latest version of the cache line. To maintain cache coherency, whenever a processor requests data from a cache line that has been modified in another processor's cache, the requesting processor's cache must also be modified to bring it up to date before the requested cache line is read and used.
Traditional multi-core systems maintain cache coherency by updating a common memory source that is off-chip, such as main memory, and then updating the requesting processor's cache line from the common memory source. Because transferring data to/from off-chip circuits is so much slower than on-chip transfers, this slows down cache-coherency updates, and negates some of the speed benefit of using on-chip cache memories.